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?2015 integrated device technology, inc. august 2015 dsc 4833/13 1 ? high-speed 3.3v 32k x 18 synchronous pipelined dual-port static ram with 3.3v or 2.5v interface cntrst r counter/ address reg. a 14r a 0r counter/ address reg. cnten r ads r cnten l ads l cntrst l dout0-8_l dout9-17_l dout0-8_r dout9-17_r b w 0 l b w 1 l b w 1 r b w 0 r i/o 0l -i/o 17l i/o 0r -i/o 17r din _l addr_l din_r addr_r oe r oe l 4833 tbl 01 ub l lb l r/ w l ce 0l ub r lb r r/ w r ce 0r ce 1r ce 1l 32k x 18 memory array clk r clk l . , a 14l a 0l functional block diagram features: true dual-port memory cells which allow simultaneous access of the same memory location high-speed clock to data access ? commercial: 4.2/5/6ns (max.) ? industrial: 5ns (max) pipelined output mode counter enable and reset features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 7.5ns cycle time, 133mhz operation (9.6 gbps bandwidth) ? fast 4.2ns clock to data out ? 1.8ns setup to clock and 0.7ns hold on all control, data, and address inputs @ 133mhz ? data input, address, byte enable and control registers ? self-timed write allows fast cycle time separate byte controls for multiplexed bus and bus matching compatibility lvttl- compatible, single 3.3v (150mv) power supply for core lvttl- compatible, selectable 3.3v (150mv)/2.5v (125mv) power supply for i/os and control signals on each port industrial temperature range (-40c to +85c) is available for selected speeds available in a 128-pin thin quad plastic flatpack (tqfp) and 208-pin fine pitch ball grid array, and 256-pin ball grid array idt70v3379s green parts available, see ordering information
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 2 description: the idt70v3379 is a high-speed32k x 18 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70v3379 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. the 70v3379 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controllable by the opt pins. the power supply for the core of the device (v dd ) remains at 3.3v. pin configuration (1,2,3,4) notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 17 16 15 14 12 13 10 9 8 7 6 5 4 3 2 1 11 a b c d e f g h j k l m n p r t u i/o 9l nc v ss nc a 2l a 4l clk l a 8l a 12l nc nc opt l nc v ss nc v ss a 1l a 5l a 9l a 13l nc v ddq l i/o 9r v ddqr v dd a 3l a 6l nc a 10l a 14l nc nc nc v ss i/o 10l nc nc i/o 11l nc v ddqr i/o 10r nc i/o 11r nc v ss v dd nc i/o 12l v dd v ss v ss nc v ss i/o 12r cntrst r nc i/o 14l v ddqr v ddql i/o 15r nc v ss nc nc nc a 11l a 7l a 0l nc i/o 7l nc i/o 6l i/o 8r ub l nc i/o 8l v ddql ce 0l ce 1l lb l cntrst l oe l i/o 0l i/o 2l i/o 1r ads r r/ w r nc i/o 16 r i/o 15l nc a 13r a 12r nc v dd clk r i/o 0r nc nc nc nc nc nc v ss a 5r a 9r ce 0r ce 1r v dd v ss nc nc nc nc nc nc a 14r a 10r ub r v ss v ddql i/o 1l i/o 2r nc nc nc nc a 11r a 7r lb r oe r v ss nc v ddql opt r nc 70v3379bf bf-208 (5) 208-pin fpbga top view (6) 4833 drw 02 i/o 14r v ddq l v ss v ddqr nc nc nc nc i/o 7r nc r/ w l nc ads l v ddq l i/o 13r cnten l v ss i/o 13 l v ss i/o 16l v ddqr v ss i/o 17 r i/o 17l v ddql v ss v dd a 8r cnten r a 6r a 3r a 1r a 2r a 0r i/o 3l i/o 4l a 4r v dd v ss v ss v ss v ddqr v ddql v ss v ddqr v ss i/o 3r i/o 4r v ss v ddqr v ss v dd v ss v dd v ss i/o 5r i/o 5l v ddqr i/o 6r v ss v ss v ddql v dd v ss v ddqr v ss v ss v dd v dd v ss v dd v ss
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 3 pin configuration (1,2,3,4) (con't.) e16 i/o 7r d16 i/o 8r c16 i/o 8l b16 nc a16 nc a15 nc b15 nc c15 nc d15 nc e15 i/o 7l e14 nc d14 nc d13 v dd c12 a 6l c14 opt l b14 v dd a14 a 0l a12 a 5l b12 a 4l c11 ads l d12 v ddqr d11 v ddqr c10 clk l b11 cntrst l a11 cnten l d8 v ddqr c8 nc a9 ce 1l d9 v ddql c9 lb l b9 ce 0l d10 v ddql c7 a 7l b8 ub l a8 nc b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 nc c5 a 13l d5 v ddql a4 nc b4 nc c4 nc d4 v dd a3 nc b3 nc c3 v ss d3 nc d2 i/o 9r c2 i/o 9l b2 nc a2 nc a1 nc b1 nc c1 nc d1 nc e1 i/o 10r e2 i/o 10l e3 nc e4 v ddql f1 i/o 11l f2 nc f3 i/o 11r f4 v ddql g1 nc g2 nc g3 i/o 12l g4 v ddqr h1 nc h2 i/o 12r h3 nc h4 v ddqr j1 i/o 13l j2 i/o 14r j3 i/o 13r j4 v ddql k1 nc k2 nc k3 i/o 14l k4 v ddql l1 i/o 15l l2 nc l3 i/o 15r l4 v ddqr m1 i/o 16r m2 i/o 16l m3 nc m4 v ddqr n1 nc n2 i/o 17r n3 nc n4 v dd p1 nc p2 i/o 17l p3 nc p4 nc r1 nc r2 nc r3 nc r4 nc t1 nc t2 nc t3 nc t4 nc p5 a 13r r5 nc p12 a 6r p8 nc p9 lb r r8 ub r t8 nc p10 clk r t11 cnten r p11 ads r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 nc p15 nc r15 nc t15 nc t16 nc r16 nc p16 i/o 0l n16 nc n15 i/o 0r n14 nc m16 nc m15 i/o 1l m14 i/o 1r l16 i/o 2r l15 nc l14 i/o 2l k16 i/o 3l k15 nc k14 nc j16 i/o 4l j15 i/o 3r j14 i/o 4r h16 i/o 5r h15 nc h14 nc g16 nc g15 nc g14 i/o 5l f16 i/o 6l f14 i/o 6r f15 nc r9 ce 0r r11 cntrst r t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 v ss f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 v ss j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 v ss j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 v ss l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 4833 drw 02c notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 70v3379bc bc-256 (5) 256-pin bga top view (6)
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 70 69 68 67 66 65 91 71 a 14l nc v ss nc io 9l io 9r v ddql v ss io 10l io 10r v ddqr v ss io 11l io 11r io 12l io 12r v dd v dd v ss v ss io 13r io 13l io 14r io 14l io 15r io 15l v ddql v ss io 16r io 16l v ddqr v ss io 17r io 17l nc nc nc a 14r a 1r a 0r opt r io 0l io 0r v ddqr v ss io 1l io 1r v ddql v ss io 2l io 2r io 3l io 3r io 4l io 4r v ss v ss v dd v dd io 5l io 5r v ddqr v ss io 7r io 7l v ddql v ss nc (v ss ) (7) io 8r io 8l nc (v ss ) (7) opt l a 0l a 1l io 6r io 6l 70v3379prf pk-128 (5) 128-pin tqfp top view (6) 4833 drw 02a a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l u b l l b l c e 1 l c e 0 l v d d v d d v s s v s s c l k l o e l r / w l a d s l c n t e n l c n t r s t l a 6 l a 5 l a 4 l a 3 l a 2 l a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r u b r l b r c e 1 r c e 0 r v d d v d d v s s v s s c l k r o e r r / w r a d s r c n t e n r c n t r s t r a 6 r a 5 r a 4 r a 3 r a 2 r 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 pin configuration (1,2,3,4) (con't.) notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 14mm x 20mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 7. in the 70v3379 (32k x 18) and 70v3389 (64k x 18), pins 96 and 99 are nc. the upgrade devices 70v3399 (128k x 18) and 70v3319 (256k x 18) assign these pins as vss. customers who plan to take advantage of the upgrade path should treat these pins as vss on the 70v3379 and 7 0v3389. if no upgrade is needed, the pins can be treated as nc.
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 5 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , cntrst = x. 3. oe is an asynchronous input signal. truth table i?read/write and enable control (1,2,3) pin names left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 14l a 0r - a 14r address i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output clk l clk r clock ads l ads r address strobe enable cnten l cnten r counter enable cntrst l cntrst r counter reset ub l - lb l ub r - lb r byte enables (9-bit bytes) v ddq l v ddqr power (i/o bus) (3.3v or 2.5v) (1) opt l opt r option for selecting v ddqx (1,2) v dd power (3.3v) (1) v ss ground (0v) 4833 tbl 01 oe clk ce 0 ce 1 ub lb r/ w upper byte i/o 9-18 lower byte i/o 0-8 mode x l h h h x high-z high-z all bytes deselected x lhhllhigh-z d in write to lower byte only x lhlhl d in high-z write to upper byte only x lhlll d in d in write to both bytes l lhhlhhigh-z d out read lower byte only l lhlhh d out high-z read upper byte only l lhllh d out d out read both bytes h l h l l x high-z high-z outputs disabled 4833 tbl 02 notes: 1. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on the i/os and controls for that port. 2. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to vih (3.3v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to vil (0v), then that port's i/os and controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v.
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 6 recommended operating temperature and supply voltage (1) absolute maximum ratings (1) truth table ii?address counter control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , be n and oe . 3. outputs are in pipelined mode: the data out will be delayed by one cycle. 4. ads and cntrst are independent of all other memory control signals including ce 0 , ce 1 and be n 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , be n. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 150mv for more than 25% of the cycle time or 4ns maximum, and is limited to < 20ma for the period of v term > v dd + 150mv. note: 1. this is the parameter t a . this is the "instant on" case tempereature. address previous address addr used clk (6) ads cnten cntrst i/o (3) mode xx0 xx l (4) d i/o (0) counter reset to address 0 an x an l (4 ) xhd i/o (n) external address used an ap ap hh h d i/o (p) external address blocked?counter disabled (ap reused) xapap + 1 h l (5) hd i/o (p+1) counter enabled?internal address generation 4833 tbl 03 grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v3.3v + 150mv industrial -40 o c to +85 o c0v3.3v + 150mv 48 33 tb l 04 symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3 ) 2.375 2.5 2.625 v v ss ground 0 0 0 v v ih input high voltage (3 ) (address & control inputs) 1.7 ____ v ddq + 125mv (2) v v ih input high voltage - i/o (3) 1.7 ____ v ddq + 125mv (2) v v il input low voltage -0.3 (1) ____ 0.7 v 4833 tb l 05a symbol rating commercial & industrial unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 4833 tbl 06 recommended dc operating conditions with v ddq at 2.5v notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v ddq + 125mv. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v il (0v), and v ddqx for that port must be supplied as indicated above. recommended dc operating conditions with v ddq at 3.3v notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v ddq + 150mv. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ih (3.3v), and v ddqx for that port must be supplied as indicated above. symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input hig h voltage (address & control inputs) (3 ) 2.0 ____ v ddq + 150mv (2) v v ih input high voltage - i/o (3) 2.0 ____ v ddq + 150mv (2) v v il input low voltage -0.3 (1 ) ____ 0.8 v 4833 tbl 05b
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 7 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 150mv) notes: 1. at v dd < - 2.0v input leakages are undefined. 2. v ddq is selectable (3.3v/2.5v) via opt pins. refer to p.4 for details. symbol parameter test conditions 70v3379s unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i lo | output leakage current ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (2 ) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (2 ) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (2 ) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (2 ) i oh = -2ma, v ddq = min. 2.0 ___ v 4833 tbl 08 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) tqfp only symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 8 pf c out (3 ) output capacitance v out = 3dv 10.5 pf 4833 tbl 07
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 8 dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 3.3v 150mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 120ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v ddq - 0.2v ce x > v ddq - 0.2v means ce 0x > v ddq - 0.2v or ce 1x - 0.2v "x" represents "l" for left port or "r" for right port. 70v3379s4 com'l only 70v3379s5 com'l & ind 70v3379s6 com'l only symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l s 375 460 285 360 245 310 ma ind s ____ ____ 285 415 ____ ____ i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com'l s 145 190 105 145 95 125 ma ind s ____ ____ 105 175 ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (1) com'l s 265 325 190 260 175 225 ma ind s ____ ____ 190 300 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v ddq - 0.2v, v in > v ddq - 0.2v or v in < 0.2v, f = 0 (2) com'ls615615615 ma ind s ____ ____ 630 ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v ddq - 0.2v (5) v in > v ddq - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com'l s 265 325 180 260 170 225 ma ind s ____ ____ 180 300 ____ ____ 4833 tbl 09
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 9 ac test conditions figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). input pulse levels (address & controls) input pulse levels (i/os) input rise/fall times input timing reference levels output reference levels output load gnd to 3 . 0v/gnd to 2.35v gnd to 3.0v/gnd to 2.35v 3ns 1.5v/1.25v 1.5v/1.25v figures 1, 2, and 3 4833 tbl 10 1.5v/1.25 50 ? 50 ? 4833 drw 03 10pf (tester) data out , 4833 drw 04 590 ? 5pf* 435 ? 3.3v data out , 833 ? 5pf* 770 ? 2.5v data out , -1 1 2 3 4 5 6 7 20.5 30 50 80 100 200 10.5pf is the i/o capacitance of this device, and 10pf is the ac test load capacitance. capacitance (pf) ? tcd (typical, ns) 4833 drw 05 ? ? ? ?
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 10 ac electrical characteristics over the operating temperature range (read and write cycle timing) (1,2) (v dd = 3.3v 150mv, t a = 0c to +70c) notes: 1. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ). 2. these values are valid for either level of v ddq (3.3v/2.5v). see page 4 for details on selecting the desired i/o voltage levels for each port. 70v3379s4 com'l only 70v3379s5 com'l & ind 70v3379s6 com'l only unit symbol parameter min. max. min. max. min. max. t cyc2 clock cycle time (pipelined) 7.5 ____ 10 ____ 12 ____ ns t ch2 clock high time (pipelined) 3 ____ 4 ____ 5 ____ ns t cl 2 clock low time (pipelined) 3 ____ 4 ____ 5 ____ ns t r clock rise time ____ 3 ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3 ____ 3ns t sa address setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t ha address hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t sc chip enable setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t hc chip enable hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t sb byte enable setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t hb byte enable hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t sw r/ w setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t hw r/ w hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t sd input data setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t hd input data hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t sad ads setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t ha d ads hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t scn cnten setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t hcn cnten hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t srst cntrst setup time 1.8 ____ 2.0 ____ 2.0 ____ ns t hrst cntrst hold time 0.7 ____ 0.7 ____ 1.0 ____ ns t oe (1) output enable to data valid ____ 4 ____ 5 ____ 6ns t ol z output enable to output low-z 0 ____ 0 ____ 0 ____ ns t ohz output enable to output high-z 1 4 1 4.5 1 5 ns t cd2 clock to data valid (pipelined) ____ 4.2 ____ 5 ____ 6ns t dc data output hold after clock high 1 ____ 1 ____ 1 ____ ns t ckhz clock high to output high-z 1 3 1 4.5 1.5 6 ns t cklz clock high to output low-z 1 ____ 1 ____ 1 ____ ns port-to-port delay t co clock-to-clock offset 6 ____ 8 ____ 10 ____ ns 4833 tbl 11
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 11 t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 4833 drw 07 q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 ub , lb (0-3) (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 4833 drw 06 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) timing waveform of a multi-device pipelined read (1,2) timing waveform of read cycle for pipelined operation (2) notes: 1. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ads = v il , cnten and cntrst = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , ub , lb = v ih following the next rising edge of the clock. refer to truth table 1. 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if ub or lb was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70v3379 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. ub , lb , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and cntrst = v ih .
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 12 clk l r/ w l address l data inl clk r r/ w r address r data outr t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t co (3) t cd2 no match valid no match match match valid 4833 drw 08 t dc r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 4833 drw 09 qn qn + 3 data out ce 1 ub , lb t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) timing waveform of left port write to pipelined right port read (1,2) notes: 1. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will be t co + 2 t cyc2 + t cd2 ). if t co > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on o pposite port will be t co + t cyc + t cd2 ). timing waveform of pipelined read-to-write-to-read ( oe = v il ) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 13 address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 4833 drw 11 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 4833 drw 10 data out qn qn + 4 ce 1 ub , lb oe t ch2 t cl2 t cyc2 t cklz t cd2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) timing waveform of pipelined read with address counter advance (1) notes: 1. ce 0 , oe , ub , lb = v il ; ce 1 , r/ w , and cntrst = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. timing waveform of pipelined read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows.
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 14 address an d 0 t ch2 t cl2 t cyc2 q 0 q 1 0 clk data in r/ w cntrst 4833 drw 13 internal (3) address ads cnten t srst t hrst t sd t hd t sw t hw counter reset write address 0 read address 0 read address 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha 1 an an + 1 (4) (5) (6) ax t sad t had t scn t hcn timing waveform of write with address counter advance (1) timing waveform of counter reset (2) notes: 1. ce 0 , ub , lb , and r/ w = v il ; ce 1 and cntrst = v ih . 2. ce 0 , ub , lb = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset cycle: a ddr 0 will be accessed. extra cycles are shown here simply for clarification. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 4833 drw 12 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd t scn t hcn
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 15 functional description the idt70v3379 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asyn- chronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70v3379s for depth expan- sion configurations. two cycles are required with ce 0 low and ce 1 high to re-activate the outputs. 4833 drw 14 idt70v3379 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 15 ce 1 ce 0 v dd v dd idt70v3379 idt70v3379 idt70v3379 control inputs control inputs control inputs control inputs ub , lb r/ w , oe , clk, ads , cntrst , cnten . depth and width expansion the idt70v3379 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v3379 can also be used in applications requiring expanded width, as indicated in figure 4. through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. figure 4. depth and width expansion with idt70v3379
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature ra nges 16 ordering information notes: 1 . contact your local sales office for industrial temp range in other speeds, packages and powers. 2. green parts available. for specific speeds, packages and powers contact your local sales office. datasheet document history 01/18/98: initial public release 03/15/99: page 10 additional notes 04/28/99: added fpbga package 06/08/99: page 2 changed package body height from 1.5mm to 1.4mm 06/11/99: page 5 deleted note 6 for table ii 07/14/99: page 2 corrected pin to t3 to v ddql 08/04/99: page 6 improved power numbers 10/04/99: upgraded speed to 133mhz, added 2.5v i/o capability 11/12/99: replaced idt logo 02/28/00: added new bga package, added full 2.5v interface capability 05/01/00: page 2 added ball pitch page 3 renamed pins page 6 made corrections to truth table page 9 changed ? numbers in figure 2 06/07/00: page 4 added information to pin and pin notes page 6 increased storage temperature parameter clarified t a parameter page 8 dc electrical parameters?changed wording from "open" to "disabled" removed note 7 on dc electrical characteristics table
6.42 idt70v3379s high-speed 3.3v 32k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature r anges 17 the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 du alporthelp@idt.com www.idt.com datasheet document history (con't) 01/10/01: page 1 changed 64k to 32k in block drawing removed preliminary status 04/10/01: added industrial temperature ranges and removed related notes 12/12/01: page 2, added date revision to pin configurations 3& 4 page 6 removed industrial temp footnote from table 04 page 8 removed industrial temp for 6ns from dc & ac electrical characteristics & 10 page 16 removed industrial temp from 6ns in ordering information added industrial temp footnote page 1 replaced tm logo with ? logo & 17 01/05/06: page 1 added green availability to features page 16 added green indicator to ordering information 02/08/06: page 5 changed footnote 2 for truth table i from ads , cnten , cntrst = v ih to ads , cnten , cntrst = x 07/25/08: page 8 corrected a typo in the dc chars table 01/19/09: page 16 removed "idt" from orderable part number 08/11/15: page 2 & 3 removed date from all of the pin configurations 206-pin fpbga, 128-pin tqfp & 256-pin pga respectively page 16 added tape & reel to ordering information ?

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